* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

E5108ASE

E500

E501

E502

E503

E504

E505

E506

E507

E50A21VBR

E50A21VBS

E50A27VBR

E50A27VBS

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